1) Field of the Invention
The present invention relates to a circuit design method and a circuit design apparatus used to design a circuit or the like on a large scale integrated circuit (LSI) or a printed wiring board (PWB).
In recent years, there has been a demand for high-speed, advanced functions and high-density in an information processing apparatus. At the same time, there has been a need to reduce a term for designing such information processing apparatus. In consequence, a design allowing a higher performance of an electronic equipment (an electric circuit) such as an LSI, PWB, etc. is expected to develop.
2) Description of the Related Art
When a packaging design for a circuit such as an LSI is carried out, information of all logic circuits about the circuit is developed into packaging design basic cells (hereinafter, abbreviated as BC occasionally), the package design (a placement design of the BCs and a routing design between the BCs) is then carried out based on a result of the development and connection information between the BCs.
The information of the logical circuit about the circuit that is an object of the design may be obtained by logically synthesizing information (Boolean expressions before the logical synthesis) inputted in a text mode (a list of character strings) using a hardware description language (hereinafter, abbreviated as HDL, occasionally) to develop it into function symbols.
The information of the logical circuit may be directly inputted as function symbols in a text mode, or directly inputted as function symbols in an interactive mode by referring to a display or the like.
Recently, circuits such as a LSI have become highly integrated. If design information of one circuit is described in a level of elements or gates, a volume of the information becomes enormous. For this, the design information is described with a logical circuit to be abstracted so that the design information may be described in a less volume of information. The packaging design is then performed on the basis of the information of the logical circuit.
The HDL or function symbol information used to input the logical circuit information is collectively termed as a high-level language from a viewpoint that they are information (language) in an abstract level (a functional description level) higher than that of an element or a gate.
Now, the HDL will be described in brief.
As a method for describing an electronic system or a logical circuit, a schematic capture has been used for a long time. The schematic capture is visible. The schematic capture therefore has an advantage that the designer can understand intuitively a configuration of the circuit. However, the schematic capture does not directly include information of a function, an operation, a timing of the operation, a delay time, etc. of the circuit so that it is impossible to fully describe the design information. If the schematic capture is processed in a computer, a high-speed process of the schematic capture is difficult since it is necessary to express the schematic capture as a graph including positional information. If a circuit such as an LSI in a larger scale is designed, the number of sheets of the schematic capture becomes too many for the designer to grasp it.
To solve the above problem, a method in a text (a language) has been developed as a method excepting the schematic capture for describing the design information of an electronic system or a logical circuit. The language used to describe an electronic system or a logical circuit is termed as a hardware description language (HDL) in a sense discriminating it from a software programming language. The HDL allows a description of a function or a configuration of an electronic system or a logical circuit. In order to design a large scale circuit such as an LSI, it is effective to enhance the design level from the logical gate level to the micro architecture level and perform a hierarchical design.
Compared with a description with the schematic capture above described, the HDL has, in general, the following features:
(1) the HDL is suitable for inputs and outputs, and processes of the computer since it is described with a list of character strings (a text mode);
(2) the HDL can be used as a part of a use description of a circuit that is an object of the design;
(3) the HDL can directly describe detailed timing information of an object of the design;
(4) the HDL provides data of less volume since there is no need to describe geometrical information of the circuit; and
(5) the HDL is suitable for automatic design since it allows easy logical synthesis or verification of a hardware.
FIG. 14 shows an example of a typical apparatus performing a package design for a circuit such as an LSI using a high-level language including the above HDL.
In FIG. 14, reference numeral 1 denotes an HLD input unit for inputting logic design information (Boolean expression information before the logical synthesis) in a text mode using the HDL. As this HLD, a VHDL [VHSIC (Very High Speed IC) Hardware Description Language] that is a standard HDL of IEEE is used, for example.
Reference numeral 2 denotes a file for storing text information (logic design information) inputted from the HDL input unit 1. Reference numeral 3 denotes logical synthesis processing unit. The logical synthesis processing unit 3 reads the text information stored in the file 2, performs a logic synthesis process on the text information to develop the text information into function symbols.
Reference numeral 4 denotes an interactive input unit for inputting high-level function symbols such as AND, OR, ADDER, etc. or connection information between these symbols as logic circuit information (intermediate information before developed into BCs) in an interactive mode. The interactive input unit 4 is configured with, for example, a terminal apparatus having a display for displaying function symbols thereon, and an input unit such as a keyboard, a mouse or the like operated by a designer to input an instruction by referring to a display on the display. Similarly, reference numeral 5 denotes a text input unit for inputting the high-level function symbols such as AND, OR, ADDER, etc. or connection information between them as logic circuit information in an interactive mode.
Reference numeral 6 denotes a file (a database) for storing a result of the process by the logic synthesis processing unit 3 and the logic circuit information from the interactive input unit 4 and the text input unit 5 as logic input information (design information in a high-level language).
Reference numeral 7 denotes a BC mapping process unit. The BC mapping process unit 7 reads out the logic input information in the functional description level stored in the file 6, develops the logic input information into BCs in a specified semiconductor process, and maps the BCs one-dimensionally in consideration of logical connectional relations. The BC mapping process unit 7 has a function (a reduction function) to delete superfluous BCs that are functionally mapped such as gates in addition to the above mapping process function.
Reference numeral 8 denotes a file for storing a result of the process by the BC mapping process unit 7. In the file 8, the logic information is stored in a state where the all logic information is developed in the BC level.
Reference numeral 9 denotes a packaging design unit for performing a package design on the basis of the information stored in the file 8. The packaging design unit 9 has a grouping process unit 10, a floor planner 11, a BC placement processing unit 12 and a BC routing process unit 13.
The grouping process unit 10 groups the developing information for the BCs stored in the file 8 depending on a page unit or a function unit, etc. The floor planner 11 performs a rough design of blocks grouped by the grouping process unit 10 in an interactive mode. The floor planner 11 is configured with a terminal apparatus having a display for displaying a condition of the rough design, etc., and an input unit such as a keyboard, a mouse, etc. operated by the designer to input an instruction by referring to a display on the display, similarly to the interactive input unit having been described above.
The BC placement processing unit 12 develops a content of each block placed in a group by the floor planner 11, initially places the BCs constituting each block on actual coordinates and performs a refining process so that the placement condition of the BCs is optimal. The BC routing process unit 13 performs a routing between the BCs placed on the predetermined coordinates by the BC placement processing unit 12 under specified conditions (a condition of wire length limitation, etc.)
Reference numeral 14 denotes a mask design data generating unit. The mask design data generating unit 14 generates design data for a mask necessary to fabricate a semiconductor (an LSI, etc.) on the basis of a result of the packaging design by the packaging design unit 9.
When a package design for a circuit such as an LSI is performed with the above structure, the logic circuit information of the circuit that is an object of the design is inputted from the HDL input unit 1 in a text mode such as the VHDL or the like and from the interactive input unit 4 or the text input unit 5 as high-level function symbols or the connection information between the symbols.
The text information from the HDL input unit 1 is once stored in the file 2, then developed into function symbols by the logic synthesis processing unit 3, and stored in the file 6 together with the information from the interactive input unit 4 or the text input unit 5.
After that, the BC mapping process unit 7 reads out the logical input information in the functional description level stored in the file 6. The logic input information is developed into BCs in a specified semiconductor process. These BCs are mapped in one-dimensionally in consideration of the logical connectional relations, and a result of the mapping process is stored in the file 8.
In the packaging design unit 9, the grouping process unit 10 first groups the developing information for the BCs stored in the file 8 depending on a page unit or a function unit, and the floor planner 11 then performs a rough design of the grouped blocks in an interactive mode.
When the rough design by the floor planner 11 is completed, the BC placement processing unit 12 develops a content of each block placed in a group by the BC placement processing unit 12. The BCs constituting each block is initially placed on the actual coordinates. A refining process to refine a condition of the placement of the BCs is performed so that the condition of the placement is optimal.
Further, the BC routing process unit 13 performs a routing between the placed BCs on the basis of the connection information under specified conditions.
By repeating the above processes in the packaging design unit 9, the BCs are most suitably placed and the BCs most suitably placed are routed.
On the basis of a result of the package design obtained as above, the mask design data generating unit 14 generates design data for a mask necessary to fabricate a circuit such as a semiconductor. The design data is sent to a factory in which the circuit is actually fabricated.
In the above-described circuit design means known in the art, the packaging design is started on the basis of information obtained by developing all logic circuit information about a circuit that is an object of the design into BCs and the connection information between the BCs. This causes an enormous volume of information treated by the packaging design unit 9. For example, a volume of the information stored in the file 4 is approximately 10 times that of the information stored in the file 2. Further, a volume of the information stored in the file 8 reaches approximately 100 times that of the above-mentioned initial information.
For this, a material necessary for a storage or the like constituting the file 8 or a period necessary for the CPU process (that is, a processing time of the packaging design unit 9) becomes enormous, the material and the processing time are thus wasteful. In consequence, a problem is that the more complicated the circuit that is an object of the design, the more difficult the packaging design processing is.